Provided by: Institute of Electrical and Electronics Engineers
In this paper, a voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, write assist and error correcting code, are selectively applied to bit positions having larger impact on the overall quality, while jointly performing voltage scaling to improve overall energy efficiency. The impact of process variations, voltage and temperature on the energy-quality tradeoff is investigated. A 28nm CMOS 32KB SRAM shows 35% energy savings at iso-quality and operates at a supply 220mV below a baseline voltage-scaled SRAM, at the cost of 1.5% area penalty.