SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA

Provided by: Science & Engineering Research Support soCiety (SERSC)
Topic: Security
Format: PDF
In this paper, the authors have done power dissipation analysis of DES algorithm, implemented on 28nm FPGA. They have used Xilinx ISE software development kit for all the observation done in this paper. Here, they have taken SSTL (Stub-Series Terminated Logic) as input-output standard. They have considered six sub-categories of SSTL (i.e. SSTL135, SSTL135-R, SSTL15, SSTL15-R, SSTL18-I and SSTL18-II) for four different WLAN frequencies (i.e. 2.4GHz, 3.6GHz, 4.9GHz and 5.9GHz). They have done analysis considering five basic powers i.e. clock power, logic power, signal power, IOs power, leakage power and total power.

Find By Topic