Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization

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Provided by: European Design and Automation Association
Topic: Storage
Format: PDF
With the constant scaling of Silicon technologies the reduction in leakage power has become one of the main challenges of modern Integrated Circuit (IC) design. In today's Systems-On-Chip (SOC) very often most of the chip area is taken by embedded SRAM, which leads in some cases to the leakage power dominating the overall power consumption. Therefore, for ultra-low-power design, suppressing leakage current becomes crucial. Sub-threshold operation is a particularly attractive solution for SRAMs, as lowering supply voltage does not only reduce the leakage in retention, but also reduces dynamic power consumption in active mode.
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