Stability Considerations of SRAM at 45nm with Adiabatic Charge of Word Line

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Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Hardware
Format: PDF
Static RAM (SRAM) of volatile memory is used to store binary data. SRAM sizing is more widely in use to increase the density of SRAM in SoC (System-on-Chip) which also uses low power supply at 45nm technology. This leads one to concentrate on stability issue of SRAM circuit in terms of noise margin though a considerable amount of power is saved. This paper discusses about a single Bit Line (BL) SRAM cell that uses a slow charging of word line during read operation there by providing better noise margin for reading, this single bit line reduces the BL capacitance.
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