Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require avoiding collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper, the authors propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture.

Provided by: Université Paris Diderot Topic: Storage Date Added: Feb 2010 Format: PDF

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