Static and Dynamic Stability Improvement Strategies for 6T CMOS Low-Power SRAMs

Provided by: edaa
Topic: Storage
Format: PDF
In this paper the authors providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. The authors consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. They use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode.

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