Provided by: Institute of Research Engineers and Doctors
Date Added: Dec 2013
SRAM cell read stability and write-ability is major concerns in CMOS technologies, due to the progressive increase in VDD and transistor scaling. In this paper, the authors studied and compared the performance of 7TN (with NMOS access transistor), 7TP (with PMOS access transistor) and conventional 6T structure. SRAM cells have been simulated in SPICE with 0.35um technology. The techniques that provide the highest data stability, the lowest power consumption, and the small layout area are identified. Both 7TN and 7TP cell provides higher write stability as compare to 6T SRAM cell (around 24% increase in SWM).