NORTH ATLANTIC UNIVERSITY UNION
In this paper, the authors focus on the impact of process variations on the estimation of static leakage power and its variability. A statistical methodology for the estimation of static leakage power dissipation due to subthreshold leakage and gate tunneling leakage in 65 nm CMOS digital circuits, in the presence of process variations, is presented. A 2-input NAND gate is used as a representative library element, whose leakage power is extensively characterized, by rigorous mixed-mode simulations. Also, an analytical model for leakage power is proposed at the gate level in terms of the device resistance data, for computational simplicity.