Statistical Thermal Evaluation and Mitigation Techniques for 3D Chip-Multiprocessors In the Presence of Process Variations

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Provided by: edaa
Topic: Hardware
Format: PDF
With increased technology scaling, wire length has become a critical factor that limits the performance of integrated circuits. Thermal issues have become critical roadblocks for achieving highly reliable Three-Dimensional (3D) integrated circuits. This paper performs both the evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip-Multi-Processors (CMPs). Furthermore, this paper provides a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed.
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