Strategies and Techniques for Optimizing Power in BIST: A Review

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Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
Power dissipation is a challenging problem in current VLSI designs. In general, the power consumption of device is more in the testing mode than in the normal system operation. Built-In Self-Test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for detecting the faults, increasing the power consumption during testing, boosting the need to add power optimizations to BIST pattern generators.
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