Structural Level Designing of Processing Elements Using VHDL
In this paper the authors involve structural design and development of processing elements using Hardware Description Language (HDL) using Altera or Xilinx softwares and implement them on Field Programmable Gate Arrays (FPGAs). In this paper, the authors will simulate and synthesize the various parameters of processing elements by using VHDL on Xilinx ISE 13.1 and target it for SPARTAN 6 FPGA board. The output is displayed by means of Liquid Crystal Display (LCD) interface. The state of each output bit is shown by using Light Emitting Diodes (LED).