International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
In this paper, a low power and high performance XNOR based 1 bit full adder cell is proposed. According to many simulations and comparisons with state of the art designs, this design demonstrates some achievement. This new full adder cell has been compared with conventional CMOS full adder cell and a few number of different logical adder cell (Transmission Gate (TG) adder, Transmission Function Adder (TFA), Complementary Pass transistor Logic (CPL) adder, N-cell adder). The most important parameters of performance are speed and power consumption. This full adder has been simulated using HSPICE with 0.18Î¼m CMOS technology at different supply voltages ranges from 1v to 3.5v with 0.5 steps.