Adder is the most fundamental component of any digital processor. The literature describes several adder configurations such as ripple carry, carry look ahead and carry skip. Application of logical effort on transistor-level analysis of different adder architecture is presented. Logical effort method is used to estimate delay and impact of different adder topologies. The tested adder topologies were 8-bit carry skip adder and 4bit ripple carry adder. The efficiency of the model is analyzed by circuit simulation using TSPICE for 1.8V, 0.18um technology.