International Journal of Scientific and Research Publication (IJSRP)
As multiplication dominates the execution time of the most Digital Signal Processing (DSP) algorithms, so there is a need of high speed multiplier. This paper presents the detailed study of different multipliers based on array multiplier, constant coefficient multiplication and multiplication based on Vedic mathematics. All these multipliers are coded in Verilog HDL (Hardware Description Language) and simulated in ModelSimXEIII6.4b and synthesized in EDA tool Xilinx ISE12. All multipliers are then compared based on LUTs (Look-Up Tables) and path delays. Results show that Vedic Urdhva Tiryakbhyam sutra is the fastest multiplier with least path delay.