Study of Chip Cost of LSI Using FinFET with Plural Number of Sidewall Channel Width
Study of chip cost of LSI using FinFET with plural number of sidewall channel width is newly described. Using the sequential fabrication of 3-4 kinds of sidewall channel chip cost of buffer circuit and CMOS cell library can be reduced by 5-5.7% compared with of that with conventional single number of sidewall channel width. Further reduction of chip cost can be realized by using simultaneous fabrication process. LSI using FinFET with plural number of sidewall channel width is promising candidate for realizing low cost high density LSI.