International journal of Engineering and Management Research (IJEMR)
In this paper, the authors present the results of a multi-level cache memory hierarchy evaluation for programmable media processors. With the continuing advances in VLSI technology, it becomes possible to support larger memory hierarchies' on-chip, but the question remains of how to most effectively use these additional silicon resources for optimizing memory performance. This paper explores that issue by evaluating the various levels of the memory hierarchy using a cache-based memory system. This evaluation examines the change in performance from varying cache parameters including the L2 cache parameters of cache size, line size, and latency, and the external memory parameters of bandwidth and latency.