International Journal of Computer Applications
In this paper, the authors discuss a rail to rail swing, mixed logic style 1-bit 28 Transistor (28T) full-adder, based on a novel architecture. The performance metrics: power, delay and Power Delay Product (PDP) of the proposed 1-bit adder are compared with other two high performance 1-bit adder architectures reported, till date. The proposed 1-bit adder has a 50% improvement in delay and 49% improvement in power-delay-product, over the two reported architectures, verified at 90nm technology. The power performance of proposed 1-bit adder and that of the two reported architecture are comparable within 8%.