Sub-threshold circuits have gained a lot of importance due to advent of ultra-low power consumption. Power dissipation and delay plays an important role in achieving optimized performance. This paper primarily focuses on Sub-Threshold Source Coupled Logic (STSCL) for building digital circuits and systems at very low voltages with optimum performance and desirable energy savings. The performance characteristics of inverter and the basic gates are operating in the sub-threshold region have been analyzed in 90 nm technology. These gates are further used to implement digital systems which would work at low supply voltages and consume less power.