Subthreshold Leakage Minimization in MOSFET Using Sleep Transistor Circuit

Provided by: Creative Commons
Topic: Hardware
Format: PDF
The excessive power consumption has become one in all the first hindrances to the more advances of CMOS integrated circuits. Low power circuit style is a crucial analysis space. There are 3 primary stimuli for low power circuit design: setting friendly inexperienced computing, battery life extension for mobile applications, and rising self-sufficing battery replacement free applications like intelligent sensing element nodes. The leakage current in MOSFET is due to sub-threshold leakage current due to parasitic PN junctions.

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