The increasing prominence of portable systems and the need to limit power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. In this paper, the authors consist the study of effect of source to substrate bias voltage (applied to an n-channel MOSFET and a p-channel MOSFET) on the leakage current component. The optimum value which minimizes the leakage current is found for n-MOS as well as p-MOS circuit (using simulation as well as mathematical analysis). This minimization of leakage current component eventually leads to a reduction in power dissipation. On application of this leakage power reduction technique, power dissipation is reduced by about 50-70%.