Massachusetts Institute of Technology
With the advent of Chip Multi-Processors (CMPs), on-chip networks are critical for providing low-power communications that scale to high core counts. With this motivation, the authors present a 64-bit, 8x8 mesh Network-on-Chip (NoC) in 90nm CMOS that: bypasses flit buffering in routers using Token Flow Control, thereby reducing buffer power along the control path and uses low-voltage-swing crossbars and links to reduce interconnect energy in the data path. These approaches enable 38% power savings and 39% latency reduction, when compared with an equivalent baseline network. An experimental 2x2 core prototype, operating at 400 MHz, validates their design.