Synthesis of 4 to 16 Reversible Decoder
Reversible logic has become an emerging field for research. The concept of reversible logic is being applied both in sequential as well as combinational circuits. This paper describes a 4 to 16 decoder using reversible logic. The decoder involves the use of Fredkin gate which is basically a reversible gate. The circuit has been implemented in Xilinx 8.2. The simulator used is Xilinx simulator. The results have been shown and verified with the irreversible 4 to 16 decoder.