Synthesis of Process Varied ASIC MIMO Decoder Architecture in 45nm CMOS

Provided by: International Journal of Innovations in Scientific and Engineering Research (IJISER)
Topic: Hardware
Format: PDF
In this paper, the authors aim to develop an ASIC to achieve the power consumption and area minimization. In this paper, the authors present an energy efficient programmable hardware accelerator that targets Multiple-Input Multiple-Output (MIMO) decoding tasks orthogonal frequency division multiplexing systems. The paper is motivated by the adoption of MIMO and OFDM by almost all existing and emerging high speed wireless data communication systems. The accelerator was fabricated in 45-nm CMOS technology and occupies a core area of 2.48 mm2.

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