Synthesis Using 65nm Library of SPI Master-Slave with Wishbone Interface

Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, the authors develop SPI master-slave with wishbone interface. It is designed to provide an interface between a microprocessor with a wishbone bus and SPI devices. With the development of the IC manufacturing, the communication between hardware devices became particularly important. The currently widely used protocols such as wishbone bus protocol let hardware devices to communicate through the appointment of the rules and match the timing for achieving the purpose of exchanging data.

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