Synthesizing Memory-Level Parallelism Aware Miniature Clones for SPEC CPU2006 and ImplantBench Workloads

Provided by: Institute of Electrical & Electronic Engineers
Topic: Storage
Format: PDF
The authors generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: huge simulation time (weeks to months) when using complete runs of modern workloads like SPEC CPU2006 having trillions of instructions on pre-silicon design models unavailability of access to their specific target applications for computer architects, as some of them are proprietary in nature and vendors hesitate to share them. They provide a detailed characterization of the SPEC CPU2006 and the ImplantBench suites based on microarchitecture-independent metrics.

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