Provided by: University of Paris 13
Date Added: Apr 2011
A single chip or a system can have more than billions of transistors, and billions of via connected through miles of interconnections. This paper aims at analyzing dynamic variations and then hard failures due to electro migration at functional level and to estimate the accuracy of the reliability aware ArchC based processor simulator. The authors use this simulator to provide the cumulative failure rate for a processor simulated at functional level, at 373MHz and 1.21V. The simulations are assumed to be under consideration of ideal environment, with no humidity and no process variability.