System Level Clock Tree Synthesis for Power Optimization

Provided by: edaa
Topic: Hardware
Format: PDF
The clock tree is the interconnect net on Systems-on-Chip (SoC) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall power dissipations are possible by optimizing the clock tree. Although these savings are already relevant at system-level, only little effort has been made to consider the clock tree at higher levels of abstraction. This paper shows how the clock-tree can be integrated into system-level power estimation and optimization. A clock tree routing algorithm is chosen, adapted to the system-level and then integrated into an algorithmic-level power optimization tool.

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