System Level Modeling of Networks-on-Chip for Power Estimation and Design Space Exploration

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Provided by: University of Rome
Topic: Hardware
Format: PDF
With a fast rising productivity and even faster rising integration densities, i.e., design productivity-gap, energy and power dissipation are critical topics in high level system design more than ever. Thermal aware system design, reliable power delivery, and the overall energy dissipation are only few crucial design properties. In this paper, the authors present a framework based on SystemC, enabling the modeling and simulation of many-core systems reverting to Networks-on-Chip (NoC) as their communicational infrastructure. The transaction level communication model is clock cycle accurate, yielding a fast yet concise functional simulation.
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