System-Level Modelling for Spinnaker CMP System

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Provided by: The University of Maine at Machias
Topic: Hardware
Format: PDF
The SpiNNaker Chip-Multi-Processor (CMP) system is a novel SoC architecture, designed specifically for large-scale neural simulations in real-time. The authors have developed a multi-chip complete system simulation for the SpiNNaker massively parallel CMP system using SystemC Transaction Level Modeling (TLM) to analyze architectural tradeoffs, verify the design, and develop/test intended applications. The model has been very helpful in understanding system-level behavior in the early stages of the design which was not possible with a Hardware Description Language (HDL) simulation because of the development time, performance and scale of simulation.
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