University of Rome
As technology reaches nanoscale order, interconnection systems account for the largest part of power consumption in Systems-on-Chip (SoC). Hence, an early and sufficiently accurate power estimation technique is needed for making the right design decisions. In this paper, the authors present a method for system-level power estimation of interconnection fabrics in Systems-on-Chip (SoC). Estimations with simple average assumptions regarding the data stream are compared against estimations considering bit level statistics in order to include low level effects like activity factors and crosstalk capacitances.