Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottleneck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, the authors examine the power/performance benefits for three different 3D stacked DRAM scenarios. Their high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-the-art industrial processes.