System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
The rapidly increasing complexity of Multi-Processor System-on-Chip (MPSoC) designs, coupled with poor global interconnect scaling in the deep sub-micron era, is making on-chip communication a critical factor affecting overall system performance and power consumption. System-on-chip communication architectures have a significant impact on the performance and power consumption of modern Multi-Processor System-on-Chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics.
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