System-level Process Variability Analysis and Mitigation for 3D MPSoCs

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Provided by: edaa
Topic: Hardware
Format: PDF
While prior research has extensively evaluated the performance advantage of moving from 2D to a 3D design style, the impact of process parameter variations on 3D designs has been largely ignored. In this paper, the authors attempt to bridge this gap by proposing a variability-aware design framework for Fully-Synchronous (FS) and Multiple Clock-Domain (MCD) 3D systems. First, they develop analytical system-level models of the impact of process variations on the performance of FS 3D designs.
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