System On Chip: Performance Analysis Of VLSI Based Networking System

Provided by: Creative Commons
Topic: Software
Format: PDF
The swell in the numeral of cores that can be incorporated on a distinct chip has forced the designer to use computer system concepts for design of System-on-Chip (SoC). The supplementary is of multiple protocols being used in the diligence at present. For larger networks, where a direct-mapped loom is not viable due to FPGA reserve limitations, a virtualized time multiplexed loom was used. Compared to the provided software reference execution, the authors direct-mapped loom achieves three orders of enormity expedite, while their virtualized time multiplexed loom achieves one to two orders of enormity expedite, depending on the set-up and router design.

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