Systematic Approach in Building Clock Tree for SOC's
System-on-Chip (SOC) design is defined as an IC, designed by arranging all individual VLSI designs so as to get full functionality for an application. The biggest problem, the authors faced in designing clock trees is skew minimization. The reasons that add to clock skew include loading mismatch at the clocked elements, mismatch in RC delay. In the present scenario, if they set target insertion delay to the tool then minimum insertion delay is target and maximum insertion delay is floating i.e., global skew is not constant.