Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

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Provided by: edaa
Topic: Hardware
Format: PDF
In this paper, the authors present a systematic comparison between two different implementations of a distributed Network-on-Chip (NoC): fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a globally asynchronous locally synchronous clusterized Multi-Processors System-on-Chip (MPSoC). The 5 relevant parameters are silicon area, network saturation threshold, communication throughput, packet latency and power consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.
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