Systemverilog Methodology for Verification of AHB-Lite Protocol

Provided by: International Journal for Technological Research in Engineering (IJTRE)
Topic: Networking
Format: PDF
In this paper, the authors describe how system Verilog-based methodologies, like Universal Verification Methodology (UVM), can be used to create a verification environment for verification of a communication bus protocol like ARM's AMBA AHB-Lite communication protocol. The verification environment is built with the test-bench components like the test, environment, agent, driver, sequencer, monitor and scoreboard. The developed environment is used for testing the AHB-Lite sequential and non-sequential (both increment and wrap of different burst sizes like 4-, 8- beat bursts) transfers. The verification process followed to verify the protocol in this paper is based on having single bus master and a slave model which communicate with each other on the AHB-Lite bus.

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