Systolic and Semi-Systolic Multiplier

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Provided by: MIT Publications
Topic: Hardware
Format: PDF
Systolic architectures (also referred to as systolic arrays) represent a network of Processing Elements (PEs) that rhythmically compute and pass the data through the system. Systolic arrays are a family of parallel computer architectures capable of using a very large number of processors simultaneously for important computations in applications such as scientific computing and signal processing. Systolic array architecture has contains 1 full adder and the latency with m per cell while semi-systolic array architecture has contains m/2 latency. The proposed multiplier has regularity, modularity and concurrency; it is suitable for VLSI implementation.
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