Targeting Code Diversity with Run-time Adjustable Issue-slots in a Chip Multiprocessor

Provided by: edaa
Topic: Hardware
Format: PDF
This paper presents an adaptable soft-core Chip Multi-Processor (CMP). The processor Instruction Set Architecture (ISA) is based on the VEX ISA. The issue-width of the processor can be adjusted at run-time (before an application starts). The processor has eight 2-issue cores that can run independently from each other. If not in use, each core can be taken to a lower power mode by gating off its source clock. Multiple 2-issue cores can be combined at run-time to form a variety of configurations of Very Long Instruction Word (VLIW) processors. The CMP is implemented in the Xilinx Virtex-6 XC6VLX240T FPGA. It has a single ISA and requires no specialized compiler support.

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