Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip Using Low-Power L2 Cache Architecture

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Provided by: RS Publication
Topic: Hardware
Format: PDF
Significant portion of cache energy in a highly associative cache is consumed during tag comparison. In this paper tag comparison is carried out by predicting both cache hit and cache miss using multistep tag comparison method. A partially tagged bloom filter is used for cache miss predictions by checking the non-membership of the addresses and hotline check for cache hit prediction by reducing the tag comparisons. Current complex embedded application employs a Multi-Processor System-on-Chip (MPSoC). A MPSoC consists of multiple processors, shared memory hierarchy and a global off-chip memory.
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