Carnegie Mellon University
Phase Change Memory (PCM) is a promising alternative to DRAM to achieve high memory capacity at low cost per bit. Adding to its better projected scalability, PCM can also store multiple bits per cell (called Multi-Level Cell, MLC), offering higher bit density. However, MLC requires precise sensing and control of PCM cell resistance, which incur higher memory access latency and energy. The authors propose a new approach to mapping and buffering data in MLC PCM to improve memory system performance and energy efficiency.