Techniques for Power Reduction in CMOS Design

Provided by: Institute of Electrical and Electronics Engineers
Topic: Hardware
Format: PDF
Recently there has been a surge of interest low-power devices and design techniques. To limit the energy and power increase in future CMOS technology generations, the supply voltage (Vdd) will have to continually scale. The amount of energy reduction depends on the magnitude of Vdd scaling. Along with Vdd scaling, the threshold Voltage (Vt) of MOS transistors will have to scale to sustain the traditional 30% gate delay reduction. Low-power electronics means that the consumption of electric power is deliberately low. These days low power devices are highly in demand because of their light weight and longer battery life. In this paper, the authors have presented different sources of power dissipation, and various techniques to lower the power dissipation in electronics devices.

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