Techniques on FPGA Implementation of 8-Bit Multipliers

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Provided by: International Journal on Computer Science and Technology (IJCST)
Topic: Hardware
Format: PDF
Multiplication is one of the basic arithmetic operations and fundamental building block in all DSP task. The objective of good multiplier is to provide a physically compact, good speed and low power consumption. To save significant power consumption in VLSI design, it is good to reduce its dynamic power that is major part of total power dissipation. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reduction of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade.
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