Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density of 3-D Integrated Circuits (ICs) might incur temperature-related problems in reliability, leakage power, system performance, and cooling cost. In this paper, the authors propose a runtime solution to maximize the performance of Chip Multi-Processors (CMPs) with 3-D stacked last-level cache memory, without thermal-constraint violation.