Tera-Scale 1D FFT With Low-Communication Algorithm and Intel R Xeon Phi Coprocessors

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
In this paper, the authors demonstrate the first tera-scale performance of Intel Xeon Phi coprocessors on 1D FFT computations. Applying a disciplined performance programming methodology of sound algorithm choice, valid performance model, and well-executed optimizations, they break the tera-flop mark on a mere 64 nodes of Xeon Phi and reach 6.7 TFLOPS with 512 nodes, which is 1.5x than achievable on a same number of Intel Xeon nodes. It is a challenge to fully utilize the compute capability presented by many-core wide-vector processors for bandwidth-bound FFT computation.
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