Ternary Logic Gates & Arithmetic Circuit

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Provided by: International Journal of Innovative Science Engineering and Technology (IJISET)
Topic: Hardware
Format: PDF
Scaling of conventional CMOS devices has reduced the device dimensions from 10mm in 1970s to 0.1um in a present day. According to ITRS (i.e. International Technology Roadmap for Semiconductors) the authors are going to face the brick wall in 2015 if they continue in the same development speed. This will not be possible for them to maintain the pace forecaste (Moore's law). This is because of the fundamental limitations of device parameter dimensions due to which performance is degrading in several ways. To overcome this and go ahead in technology, one must look into new devices those can be scaled down to come up with other solutions.
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