Institute of Electrical & Electronic Engineers
Test-Access Mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based System-on-Chip (SoC). Such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on Through-Silicon Vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. The authors present an optimization technique for minimizing the test time for 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth.