Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling

Provided by: edaa
Topic: Hardware
Format: PDF
A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper. A broadcast scan based test compression algorithm for parallel testing of cores with multiple scan chains is used to reduce the test data of the SoC. Unlike other test compression schemes, the proposed algorithm doesn't require specialized test generation or fault simulation and is applicable with Intellectual Property (IP) cores. The core testing schedule with compression enabled is decided using a generalized strip packing algorithm.

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