Test Generation for Clock-Domain Crossing Faults in Integrated Circuits

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Provided by: edaa
Topic: Hardware
Format: PDF
Clock-Domain Crossing (CDC) faults are a serious concern for high-speed, multi-core integrated circuits. Even when robust design methods based on synchronizers and design verification techniques are used, process variations can introduce subtle timing problems that affect data transfer across clock-domain boundaries for fabricated chips. The authors present a test generation technique that leverages commercial ATPG tools, but introduces additional constraints, to detect CDC faults. They also present HSpice simulation data using a 45 nm technology to quantify the occurrence of CDC faults at clock-domain boundaries.
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