Test Method for Encoder and Decoder Circuits used in Communication Networks

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Provided by: International Journal of Electrical, Electronics and Computer Engineering (IJEECE)
Topic: Networking
Format: PDF
Transistor density on integrated circuit doubles every two year. For decades, Intel has met this challenge and has made Moore's Law a reality. As transistor counts climb so does the ability to increase device complexity and integrate many capabilities onto a chip. With increase in the functional complexity on the chip, accessing of internal sub - circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip is also becoming difficult, very time consuming and costly process with increasing cost.
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